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| TAS5026A TM Six Channel Digital Audio PWM Processor Data Manual January 2004 DAV Digital Audio/Speaker SLES068A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303, Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Contents Contents Section 1 Page 1 1 2 3 4 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Clock and Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Clock Master/Slave Mode (M_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 Clock Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.4 Clock Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.6 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.7 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Reset, Power Down, and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 Reset--RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 Power Down--PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3 General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.1 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.3 Automute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.4 Individual Channel Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.5 De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.1 Clipping Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.2 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.3 Individual Channel Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.4 PWM DC-Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.5 Interchannel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5 I2C Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5.1 Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5.2 Multiple-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.5.3 Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.5.4 Multiple-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Control Interface Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Status Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register 0 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Recovery Register (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automute Delay Register (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC-Offset Control Registers (0x06-0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 26 26 27 27 28 28 3 February 2003--Revised January 2004 SLES068A iii List of Illustrations 3.8 3.9 4 Interchannel Delay Registers (0x0C-0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Individual Channel Mute Register (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 31 31 32 35 37 37 37 37 37 37 38 38 38 42 45 47 48 48 48 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Data Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Changing Between Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Static Digital Specifications Over Recommended Operating Conditions . . . . . . . . . . . . . . 5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 TAS5026A/TAS5110 System Performance Measured at the Speaker Terminals Over Recommended Operating Conditions (Fs = 48 kHz) . . . . . . . . . . . . . . . . 5.4 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Command Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Serial Control Port--I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Serial Audio Interface Clock Master and Slave Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 7 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Appendix A--Volume Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 List of Illustrations Figure Title Page 2-1 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-2 External PLL Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-3 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2-4 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2-5 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2-6 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2-7 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2-8 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2-9 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2-10 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2-11 De-Emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2-12 PWM Outputs and H-Bridge Driven in BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2-13 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2-14 Single-Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2-15 Multiple-Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2-16 Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 iv SLES068A February 2003--Revised January 2004 List of Tables 2-17 Multiple-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 RESET During System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal . . . . . . . . . . . . . . . . . 4-3 Changing the Data Sample Rate Using the DBSPD Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Changing the Data Sample Rate Using the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal . . . . . . . . . . . . . . 4-6 Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Changing Between Master and Slave Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Power-Down and Power-Up Timing--RESET Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Power-Down and Power-Up Timing--RESET Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Right-Justified, I2S, Left-Justified Serial-Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Right, Left, and I2S Serial-Mode Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Serial Audio Ports Master-Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 DSP Serial-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 DSP Serial-Port Expanded Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Typical TAS5026A Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 TAS5026A Serial Audio Port--Slave-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 TAS5026A Serial Audio Port--Master-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 31 32 33 33 34 35 36 38 39 40 41 41 42 43 43 43 44 44 45 45 47 48 48 List of Tables Table Title Page 2-1 Normal-Speed, Double-Speed, and Quad-Speed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-2 Master and Slave Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-3 LRCLK and MCLK_IN Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-4 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2-5 Supported Word Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2-6 Device Outputs During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-7 Values Set During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-8 Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-9 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2-10 De-Emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2-11 Device Outputs During Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3-1 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-2 General Status Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-3 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-4 System Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-5 System Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3-6 Error Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 February 2003--Revised January 2004 SLES068A v List of Tables 3-7 Automute Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DC-Offset Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Six Interchannel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Individual Channel Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 29 vi SLES068A February 2003--Revised January 2004 Introduction 1 Introduction The TAS5026A is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5026A is designed to drive up to six digital power devices to provide six channels of digital audio amplification. The digital power devices can be six conventional monolithic power stages (such as TAS5110) or six discrete differential power stages using gate drivers and MOSFETs. The TAS5026A has six independent volume controls and mute. The device operates in AD mode. This all-digital audio system contains only two analog components in the signal chain--an LC low-pass filter at each speaker terminal and can provide up to 96-dB SNR at the speaker terminals. The TAS5026A has a wide variety of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified, or DSP (16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample rates. The TAS5026A was designed for home theater applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver, A/V receiver, or TV sets. 1.1 Features * * TI PurePath Digital Audio Amplifier High Quality Audio - 96-dB SNR - <0.1% THD+N Six-Channel Volume Control - Patented Soft Volume - Patented Soft Mute 16-, 20-, or 24-Bit Input Data Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz Supports Master and Slave Modes 3.3-V Power Supply Operation Economical 64-Pin TQFP Package Digital De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz Clock Oscillator Circuit for Master Modes Low Jitter Internal PLL Soft Volume and Mute Update * * * * * * * * * * Equibit and PurePath Digital are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. SLES068A--February 2003--Revised January 2004 TAS5026A 1 Introduction 1.2 Functional Block Diagram VREGA_CAP VREGB_CAP VREGC_CAP DVDD_PWM DVSS_PWM DVDD_RCL DVSS_RCL AVDD_PLL AVSS_PLL Power Supply PWM Section MCLK_IN XTAL_OUT XTAL_IN DBSPD M_S PLL_FLT_OUT PLL_FLT_RET SCLK LRCLK MCLKOUT SDIN1 SDIN2 SDIN3 DM_SEL1 DM_SEL2 Clock, PLL and Serial Data I/F Signal Processing PWM Ch. PWM Ch. PWM_AP_1 PWM_AM_1 VALID_1 PWM_AP_2 PWM_AM_2 VALID_2 Output Control PWM AP_3 PWM AM_3 VALID_3 PWM Ch. Auto Mute De-Emphasis Soft Volume Error Recovery Soft Mute Clip Detect PWM_AP_4 PWM_AM_4 VALID_4 SDA SCL CSO Serial Control I/F PWM Ch. PWM_AP_5 PWM_AM_5 PWM Ch. RESET PDN Reset, Pwr Dwn and Status PWM Ch. CLIP MUTE ERR_RCVRY VALID_5 PWM_AP_6 PWM_AM_6 VALID_6 2 TAS5026A SLES068A--February 2003--Revised January 2004 Introduction 1.3 Terminal Assignments PAG PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC MCLK_IN AVDD_PLL PLL_FLT_OUT PLL_FLT_RET AVSS_PLL NC DVSS1 RST ERR_RCVRY MUTE PDN SDA SCL CS0 DVSS1 AVDD_OSC XTL_IN XTL_OUT AVSS_OSC DVSS PWM_AP_1 PWM_AM_1 VALID_1 PWM_AP_2 PWM_AM_2 VALID_2 PWM_AP_3 PWM_AM_3 VALID_3 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DVDD_RCL DVSS_RCL NC DVDD_PWM DVSS_PWM PWM_AP_4 PWM_AM_4 VALID_4 PWM_AP_5 PWM_AM_5 VALID_5 PWM_AP_6 PWM_AM_6 VALID_6 NC NC DBSPD CLIP SDIN1 SDIN2 SDIN3 MCLK_OUT SCLK LRCLK DVDD DVSS1 NC DEM_SEL2 DEM_SEL1 M_S DVSS1 DVSS1 SLES068A--February 2003--Revised January 2004 TAS5026A 3 Introduction 1.4 Ordering Information T AS 5026A PAG Texas Instruments Audio Solutions Device Number Package Type AVAILABLE OPTIONS PACKAGE TA 0C to 70C PLASTIC 64-PIN TQFP (PAG) TAS5026APAG 1.5 Terminal Functions TERMINAL NAME NO. 64 3 61 6 18 15 17 29 28 45 48 25 60 44 47 8, 26, 31, 32 10 24 30 2 22 11 FUNCTION P P O P O I I I I P P P I P P P I I/O I I O I DESCRIPTION Analog power supply for internal oscillator cells 3.3-V analog power supply for PLL Analog ground for internal oscillator cells Analog ground for PLL Digital clipping indicator, active low I2C device address select. This is an active high pin. Sample rate is double speed (88.2 kHz or 96 kHz), active high De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz De-emphasis select bit 2, 10 = 48 kHz, 11 = undefined (none) 3.3-V digital power supply for PWM 3.3-V digital power supply for re-clocker 3.3-V digital power supply for digital core and most of I/O buffers Voltage regulator enable, active low Digital ground for PWM Digital ground for re-clocker Digital ground for digital core and most of I/O buffers Error recovery, active low Serial audio data left/right clock (sampling rate clock) (input when M_S = 0; output when M_S = 1) Master/slave mode input signal (master = 1, slave = 0) MCLK input, slave mode MCLK output buffered system clock output M_S = 1; otherwise set to 0 Mute input signal, active low AVDD_OSC AVDD_PLL AVSS_OSC AVSS_PLL CLIP CS0 DBSPD DM_SEL1 DM_SEL2 DVDD_PWM DVDD_RCL DVDD DVSS DVSS_PWM DVSS_RCL DVSS1 ERR_RCVRY LRCLK M_S MCLK_IN MCLK_OUT MUTE I = input; O = output; I/O = input/output; P = power 4 TAS5026A SLES068A--February 2003--Revised January 2004 Introduction TERMINAL NAME NC NO. 1, 7, 27, 33, 34, 36, 49, 50 12 4 5 58 55 52 42 39 36 59 56 53 43 40 37 9 14 23 13 19 20 21 57 54 51 41 38 35 63 FUNCTION -- No connection DESCRIPTION PDN PLL_FLT_OUT PLL_FLT_RET PWM_AM_1 PWM_AM_2 PWM_AM_3 PWM_AM_4 PWM_AM_5 PWM_AM_6 PWM_AP_1 PWM_AP_2 PWM_AP_3 PWM_AP_4 PWM_AP_5 PWM_AP_6 RST SCL SCLK SDA SDIN1 SDIN2 SDIN3 VALID_1 VALID_2 VALID_3 VALID_4 VALID_5 VALID_6 XTL_IN I I I O O O O O O O O O O O O I I I/O I/O I I I O O O O O O I Power down. This signal is active low. PLL external filter PLL external filter PWM 1 output (differential -); {Positive H-bridge side} PWM 2 output (differential -); {Positive H-bridge side} PWM 3 output (differential -); {Positive H-bridge side} PWM 4 output (differential -); {Positive H-bridge side} PWM 5 output (differential -); {Positive H-bridge side} PWM 6 output (differential -); {Positive H-bridge side} PWM 1 output (differential +); {Positive H-bridge side} PWM 2 output (differential +); {Positive H-bridge side} PWM 3 output (differential +); {Positive H-bridge side} PWM 4 output (differential +); {Positive H-bridge side} PWM 5 output (differential +); {Positive H-bridge side} PWM 6 output (differential +); {Positive H-bridge side} System reset input. This signal is an active low. I2C clock signal Serial audio data clock (master mode = output, slave mode = input) I2C data signal Serial audio data 1 input Serial audio data 2 input Serial audio data 3 input Output indicating validity of PWM outputs, channel 1, active high Output indicating validity of PWM outputs, channel 2, active high Output indicating validity of PWM outputs, channel 3, active high Output indicating validity of PWM outputs, channel 4, active high Output indicating validity of PWM outputs, channel 5, active high Output indicating validity of PWM outputs, channel 6, active high Crystal or TTL level clock input XTL_OUT 62 O Crystal output (not for external usage) I = input; O = output; I/O = input/output; P = power SLES068A--February 2003--Revised January 2004 TAS5026A 5 Introduction 6 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview 2 Architecture Overview The TAS5026A is composed of six functional elements: * * * * * * Clock, PLL, and serial data interface (I2S) Reset/power-down circuitry Serial control interface (I2C) Signal processing unit Pulse-width modulator (PWM) Power supply 2.1 Clock and Serial Data Interface The TAS5026A clock and serial data interface contain an input serial data slave and the clock master/ slave interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The serial data interfaces support left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data interface supports the DSP protocol for 16 bits and the I2S protocol for 24 bits. The TAS5026A can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock), and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The TAS5026A is a clock master when it generates these clocks and is a clock slave when it receives these clocks. The TAS5026A is a synchronous design that relies upon the master clock to provide a reference clock for all of the device operations and communication via the I2C. When operating as a slave, this reference clock is MCLK_IN. When operating as a master, the reference clock is either a TTL clock input to XTAL_IN or a crystal attached across XTAL_IN and XTAL_OUT. The clock and serial data interface has two control parameters: data sample rate and clock master or slave. 2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (X02). The data sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double speed, and quad speed. Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits in the system control register 0 (x02) through the serial control interface. The PWM is placed in double speed mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register. Quad-speed mode is auto detected supported in slave mode and invoked using the I2C serial control interface in master mode. In slave mode, if the TAS5026A is not in double speed mode, quad-speed mode is automatically detected when MCLK_IN is 128Fs. In master mode, the PWM is placed in quad-speed mode by setting the quad-speed bit in the system control register through the serial control interface. If the master clock is well behaved during the frequency transition (the high or low clock periods are not less than 20 ns), then a simple speed selection is simply performed by setting the DBSPD terminal or the serial control register. When the sample rate is changed, the TAS5026A temporarily suspends processing, places the PWM outputs in a hard mute (PWM P outputs low; PWM M outputs high, and all VALID signals low), resets all internal processes, and suspends all I2C operations. The TAS5026A then performs a partial re-initialization and noiselessly restarts the PWM output. The TAS5026A preserves all control register settings throughout this sequence. If desired, the sample rate change can be performed while mute is active to provide a completely silent transition. The timing of this control sequence is shown in Section 4. SLES068A--February 2003--Revised January 2004 TAS5026A 7 Architecture Overview If the master clock input can encounter a high clock or low clock period of less than 20 ns while the data rates are changing, then RESET should be applied during this time There are two recommended control procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences are shown in Section 4. Table 2-1. Normal-Speed, Double-Speed, and Quad-Speed Operation QUAD-SPEED CONTROL REGISTER BIT 0 0 1 0 1 DBSPD TERMINAL OR CONTROL REGISTER BIT 0 1 0 0 1 MODE Master or slave Master or slave Master or slave Slave Master or slave SPEED SELECTION Normal speed Double speed Quad speed Quad speed if MCLK_IN = 128 Fs Error 2.1.2 Clock Master/Slave Mode (M_S) Clock master and slave mode can be invoked using the M_S (master slave) terminal. This terminal specifies the default mode that is set immediately following a device RESET. The serial data interface setting permits the clock generation mode to be changed during normal operation. The transition to master mode occurs: * Following a RESET when M_S terminal has a logic high applied The transition to slave mode occurs: * Following a RESET when M_S terminal has a logic low applied 2.1.3 Clock Master Mode When M_S = 1 following a RESET, the TAS5026A provides the master clock, SCLK, and LRCLK to the rest of the system. In the master mode, the TAS5026A outputs the audio system clocks MCLK_OUT, SCLK, and LRCLK. The TAS5026A device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL). The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK frequency is the data sample rate. 2.1.3.1 Crystal Type and Circuit In clock master mode the TAS5026A can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case, the TAS5026A uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5026A as shown in Figure 2-1. 8 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview TAS5026A OSC MACRO XO C2 XI C1 rd AVSS rd = Drive level control resistor - crystal vendor specified CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal) CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF) Example: Vendor recommended CL = 18 pF, CS = 3 pF C1 = C2 = 2 x (18-3) = 30 pF Figure 2-1. Crystal Circuit 2.1.4 Clock Slave Mode In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5026A. The master clock is supplied through the MCLK_IN terminal. As in the master mode, the TAS5026A device develops its internal timing from the internal phase-locked loop (PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data sample rate. The LRCLK frequency is the data sample rate. The TAS5026A does not require any specific phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5026A monitors the relationship between MCLK, SCLK and LRCLK. The TAS5026A detects if any of the three clocks are absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error, or if the MCLK frequency is changing substantially with respect to the PLL frequency. When a clock error is detected, the TAS5026A performs a clock error management sequence. The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard mute (PWM_P outputs are low; PWM_M outputs are high, and all VALID signals are low), resets all internal processes, sets the volumes to mute, and suspends all I2C operations. When the error condition is corrected, the TAS5026A exits the clock error sequence by performing a partial re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in the volume control registers. This sequence is performed over a 60-ms interval. The TAS5026A preserves all control register settings that were set prior to the clock interruption. If a clock error occurs while the ERR_RCVRY terminal is asserted (low), the TAS5026A performs the error management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering a mute/unmute sequence by asserting and releasing MUTE either by using the terminal, the system control register X01 D4, or the individual channel mute register D5-D0. Alternatively, the TAS5026A can be prevented from entering the latched mute state following a clock error when the ERR_RCVRY terminal or the error recovery I2C command (register X03 bit D2) is active by writing x7F to the individual error recovery register (x04) and a x84 to x1F (a feature enable register). SLES068A--February 2003--Revised January 2004 TAS5026A 9 Architecture Overview Table 2-2. Master and Slave Clock Modes DESCRIPTION Internal PLL, master, normal speed Internal PLL, master, normal speed Internal PLL, master, normal speed Internal PLL, master, double speed Internal PLL, master, double speed Internal PLL, master, quad speed Internal PLL, master, quad speed Internal PLL, slave, normal speed Internal PLL, slave, normal speed Internal PLL, slave, normal speed Internal PLL, slave, double speed Internal PLL, slave, double speed Internal PLL, slave, quad speed || Internal PLL, slave, quad speed || M_S 1 1 1 1 1 1 1 0 0 0 0 0 0 DBSPD 0 0 0 1 1 0 0 0 0 0 1 1 0 XTL_IN (MHz) 8.192 11.2896 12.288 MCLK_IN (MHz) 22.5792 24.576 22.5792 24.576 8.192 11.2896 12.288 22.5792 24.576 22.5792 SCLK (MHz)k 2.048 2.8224 3.072 5.6448 6.144 11.2896 12.288 2.0484 2.8224 3.072 5.6448 6.144 11.2896 LRCLK (kHz) 32 44.1 48 88.2 96 176.4 192 32 44.1 48 88.2 96 176 192 MCLK_OUT (MHz)# 8.192 11.2896 12.288 22.5792 24.576 22.5792 24.576 Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND 0 0 24.576 12.288 A crystal oscillator is connected to XTL_IN. MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided. External MCLK_IN connected to MCLK_IN_IN input SCLK and LRCLK are outputs when M_S = 1, and inputs when M_S = 0. # MCLK_OUT is driven low when M_S = 0. || Quad-speed mode is detected automatically. kSCLK can be 48 or 64 times Fs Table 2-3. LRCLK and MCLK_IN Rates NORMAL SPEED (kHz) LRCLK MCLK_IN 1 Fs 256 Fs 32 8,192 44.1 11,289.6 48 12,288 1 Fs 256 Fs DOUBLE SPEED (kHz) 64 16,384 88.2 22,579.2 96 24,576 QUAD SPEED (kHz) 1 Fs 128 Fs 176.4 22,579.2 192 24,576 2.1.5 PLL External Filter A low jitter PLL produces the internal timing of the TAS5026A (when in master mode), the master clock, SCLK, and LRCLK. Connections for the PLL external filter are provided through PLL_FLT_OUT and PLL_FLT_RET as shown in Figure 2-2. PLL_FLT_OUT 220 4.7 nF TAS5026A 47 nF PLL_FLT_RET Figure 2-2. PLL External Filter 10 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview 2.1.6 DCLK DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5026A uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I2C addressable registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency is drifting. Table 2-4 DCLK shows the relationship between Sample Rate, MCLK, and DCLK. Table 2-4. DCLK Fs (kHz) 32 44.1 48 88 96 192 MCLK (MHz) 8.1920 11.2896 12.2880 22.5280 24.5760 49.1520 DCLK (MHz) 65.5360 90.3168 98.3040 90.1120 98.3040 98.3040 DCLK Period (ns) 15.3 11.1 10.2 11.1 10.2 10.2 2.1.7 Serial Data Interface The TAS5026A operates as a slave only/receive only serial data interface in all modes. The TAS5026A has three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The serial audio data is in MSB first; 2s complement format. The serial data interfaces of the TAS5026A can be configured in right justified, I2S, left-justified, or DSP modes. This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample rates. The serial data interface format is specified using the data interface control register. The supported word lengths are shown in Table 2-5. During normal operating conditions if the serial data interface settings change state, an error recovery sequence is initiated. Table 2-5. Supported Word Lengths DATA MODES Right justified, MSB first Right justified, MSB first Right justified, MSB first I2S I2S I2S Left justified, MSB first DSP frame WORD LENGTHS 16 20 24 16 20 24 24 16 MOD2 0 0 0 0 1 1 1 1 MOD1 0 0 1 1 0 0 1 1 MOD0 0 1 0 1 0 1 0 1 SLES068A--February 2003--Revised January 2004 TAS5026A 11 Architecture Overview 2.1.7.1 I2S Timing I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5026A masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock. 2-Channel I2S (Philips Format) Stereo Input 32 Clks 32 Clks LRCLK (Note Reversed Phase) Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 0 5 4 1 0 9 8 5 4 1 0 LSB MSB LSB 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 Figure 2-3. I2S 64-Fs Format 2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size) 24 Clks LRCLK Left Channel Right Channel 24 Clks SCLK SCLK MSB 24-Bit Mode 23 22 21 20 19 20-Bit Mode 19 18 17 16 15 16-Bit Mode 15 14 13 12 11 1 0 5 4 1 0 8 7 5 4 3 2 LSB MSB LSB 1 0 23 22 21 20 19 8 7 5 4 3 2 1 19 18 17 16 15 5 4 1 0 15 14 13 12 11 1 0 Figure 2-4. I2S 48-Fs Format 12 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview 2.1.7.2 Left-Justified Timing Left-justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5026A masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock. 2-Channel Left-Justified Stereo Input 32 Clks LRCLK Left Channel LRCLK Right Channel 32 Clks SCLK MSB 24-Bit Mode 23 22 9 8 5 4 1 0 LSB MSB LSB 23 22 9 8 5 4 1 0 NOTE: All data presented in 2s complement form with MSB first. Figure 2-5. Left-Justified 64-Fs Format 2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size) 24 Clks LRCLK Left Channel Right Channel 24 Clks SCLK MSB 24-Bit Mode 23 22 21 20 19 9 8 5 4 3 2 1 LSB MSB LSB 0 23 22 21 20 19 9 8 5 4 3 2 1 0 Figure 2-6. Left-Justified 48-Fs Format 2.1.7.3 Right-Justified Timing Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5026A masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock. SLES068A--February 2003--Revised January 2004 TAS5026A 13 Architecture Overview 2-Channel Right-Justified (Sony Format) Stereo Input 32 Clks LRCLK Left Channel Right Channel 32 Clks SCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 15 14 1 19 18 15 14 1 LSB MSB LSB 0 23 22 19 18 15 14 1 0 0 19 18 15 14 1 0 0 15 14 1 0 NOTE: All data presented in 2s complement form with MSB first. Figure 2-7. Right-Justified 64-Fs Format 2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size) 24 Clks LRCLK Left Channel Right Channel 24 Clks SCLK MSB 24-Bit Mode 23 22 21 20 19 18 20-Bit Mode 19 18 16-Bit Mode 15 14 9 8 1 15 14 9 8 1 15 14 9 8 1 LSB MSB LSB 0 23 22 21 20 19 18 15 14 9 8 1 0 0 19 18 15 14 9 8 1 0 0 15 14 9 8 1 0 NOTE: All data presented in 2s complement form with MSB first. Figure 2-8. Right-Justified 48-Fs Format 14 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview 2.1.7.4 DSP Mode Timing DSP mode timing uses an LRCLK to define when data is to be transmitted for both channels. A bit clock running at 64 x Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5026A masks unused trailing data bit positions. SCLK 64 SCLKS LRCLK MSB SDIN LSB MSB LSB 16 Bits Left Channel 16 Bits Right Channel 32 Bits Unused Figure 2-9. DSP Format 2.2 Reset, Power Down, and Status The reset, power down, and status circuitry provides the necessary controls to bring the TAS5026A to the initial inactive condition, achieve low power standby, and report system status. 2.2.1 Reset--RESET The TAS5026A is placed in the reset mode by setting the RESET terminal low. RESET is an asynchronous control signal that restores the TAS5026A to its default conditions, sets the valid 1-6 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation (there is no ramp down). As long as the RESET terminal is held low, the device is in the reset state. During reset, all I2C and serial data bus operations are ignored. Table 2-6 shows the device output signals while RESET is active. Upon the release of RESET, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when RESET is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes active. During device initialization all controls are reset to their initial states. Table 2-7 shows the control settings that are changed during initialization. RESET should be applied during power-up initialization or while changing the master slave clock states. SLES068A--February 2003--Revised January 2004 TAS5026A 15 Architecture Overview Table 2-6. Device Outputs During Reset SIGNAL Valid 1-Valid 6 PWM P-outputs PWM M-outputs MCLKOUT SCLK SCLK LRCLK LRCLK SDA CLIP MODE All All All All Master Slave Master Slave All All SIGNAL STATE Low Low Low Low Low Signal input Low Signal input Signal input High Because the RESET is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. However, when RESET is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. If a completely quiet reset sequence is desired, MUTE should be applied before applying RESET. Table 2-7. Values Set During Reset CONTROL Volume MCLK_IN frequency Master/slave mode Automute De-emphasis DC offset Interchannel delay 0 dB 256 M_S terminal state Enabled None 0 Each channel is set to a default value SETTING 2.2.2 Power Down--PDN The TAS5026A can be placed into the power-down mode by holding the PDN terminal low. When power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation (there is no ramp down). The valid 1-6 outputs are immediately asserted low and the PWM outputs are placed in the hard mute state. PDN initiates device power down without clock inputs. As long as the PDN terminal is held low--the device is in the power-down (hard mute) state. During power down, all I2C and serial data bus operations are ignored. Table 2-8 shows the device output signals while PDN is active. Table 2-8. Device Outputs During Power Down SIGNAL Valid 1-Valid 6 PWM P-outputs PWM M-outputs MCLKOUT SCLK SCLK LRCLK LRCLK SDA CLIP MODE All All All All Master Slave Master Slave All All SIGNAL STATE Low Low Low Low Low Signal input Low Signal input Signal input High To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior to bringing PDN high, RESET must be brought low for a minimum of 50 ns. 16 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. However, when PDN is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. If a completely quiet reset sequence is desired, MUTE should be applied before applying PDN. 2.2.2.1 Recovery Time Options To support the requirements of various system configurations, the TAS5026A can come up to the normal state after either a long (100 ms) or a short (5 ms) delay. 1. In the first case, a slow system (95 ms to 100 ms) start-up occurs at the end of the power-down sequence when: RESET is high for at least 16 MCLK_IN periods before PDN goes high. 2. Otherwise a fast (4 ms to 5 ms) start-up occurs. NOTE: If MCLK_IN is not active when both of these signals are released high, then a fast (4 ms to 5 ms) start-up occurs once MCLK_IN becomes active. 2.2.3 General Status Registers The general status register is a read only register. This register provides an indication when a volume update is in progress or one of the channels is inactive. The device id can be read using this register. Volume update is in progress--Whenever a volume change is in progress due to a volume update command or mute, this status bit is high. Device identification code--The device identification code, 1 0011, is displayed. No internal errors (all valid signals are high)--When there are no internal errors in the TAS5026A and all outputs are valid, this status bit is high. One or more valid signals are inactive--If low, one or more channels of the TAS5026A are not outputting data. The Valid signals for those channels are inactive. This can be produced by one of three causes: * * * * * One or more of the clock signals are in error Error recover is active (low) The automute has silenced one or more channels that are receiving 0 inputs Mute has been set Volume control has been set to full attenuation If this signal is high, the TAS5026A is outputting data on all channels. 2.2.4 Error Status Register The error status register indicates historical information on control signal changes and clock errors. This register latches these indications when they occur. The indications are cleared by writing a 00(Hex) to the register. This register is intended as a diagnostic tool to be used only when the system is not operating correctly. This is because the error status bits are set when the data rate, serial data interface format, or master/slave mode is changed. As a result, this register indicates an error condition even though the system is operating normally. This register should only be used while diagnosing transient error conditions. Any clock error or control signal terminal change which occurs since the last time the error status register was cleared is displayed. In using this register, the first step is to initialize the device and verify that all of the clock signals are active. Then this register should be cleared by writing a 00(Hex). At this point, the register indicates any errors or control signal changes. SLES068A--February 2003--Revised January 2004 TAS5026A 17 Architecture Overview This register indicates an error condition by a high for the following conditions: * * * * * * * FS ERROR A control terminal change has occurred (M_S, DBLSPD) LRCLK error MCLK_IN count error DCLK phase error with respect to MCLK_IN MCLK_IN phase error with respect to DCLK PWM timing error If all bits of the register are low, no errors have occurred and no control terminals changed. There is no one-to-one correspondence of clock error indication to a system error condition. A particular system error can be indicated by one or more error indications in this register. The system error conditions and the reported errors are as follows: There is no correct number of MCLKs per LRCLK: * * * FS error has occurred LRCLK error MCLK_IN count error LRCLK is absent: * LRCLK error MCLK is the wrong frequency, changing frequency, or absent: * * * DCLK phase error with respect to MCLK MCLK phase error with respect to DCLK PWM timing error SCLK is the wrong frequency or absent: * SCLK error 2.3 Signal Processing This section contains the signal processing functions that are contained in the TAS5026A. The signal processing is performed using a high-speed 24-bit signal processing architecture. The TAS5026A performs the following signal processing features: * Individual channel soft volume with a range of 24 dB to -114 dB plus mute * Soft mute * Automute * 50-s/15-s de-emphasis filter supported in the sampling rates 32 kHz, 44.1 kHz, and 48 kHz 2.3.1 Volume Control The gain of each output can be adjusted by a soft digital volume control for each channel. Volume adjustments are performed using a soft gain update s-curve, which is approximated using a second order filter fit. The curve fit is performed over a transition interval between 41 ms and 65 ms. The volume of each channel can be adjusted from mute to -114 dB to 24 dB in 0.5 dB steps. Because of the numerical representation that is used to control the volume, at very low volume levels the step size increases for gains that are less than -96 dB. The default volume setting following power up or reset is 0 dB for all channels. The step size adjustment is linear down to approximately -90 dB, see see Figure 2-10. 18 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview STEP SIZE vs ATTENUATION (GAIN) 6.0 5.5 5.0 4.5 4.0 Step Size - dB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 Attenuation (Gain) - dB Figure 2-10. Attenuation Curve The volume control format for each channel is expressed in 8 bits. The volume for each channel is set by writing 8 bits via the serial control interface. The MSB bit is written first as in the bit position 0 (LSB position). The volume for each channel can be set using a single or multiple address write operation to the volume control register via the serial control interface. Changing the volume of all six channels requires that 6 registers be updated. To coordinate the volume adjustment of multiple channels simultaneously, the TAS5026A performs a delayed volume update upon receiving a volume change command. Following the completion of the register volume write operations, the TAS5026A waits for 5 ms for another volume command to be given. If no volume command is issued in that period of time, the TAS5026A starts adjusting the volume of the channels that received volume settings. While a volume update is being performed, the system status register indicates that the update is in progress. During the update, all subsequent volume control setting requests that are sent to the TAS5026A are received and stored as a single next value for a subsequent update. If more than one volume setting request is sent, only the last is retained. Table 2-9. Volume Register VOLUME REGISTER D7 Vol Bit 7 D6 Vol Bit 6 D5 Vol Bit 5 D4 Vol Bit 4 D3 Vol Bit 3 D2 Vol Bit 2 D1 Vol Bit 1 D0 Vol Bit 0 2.3.2 Mute The application of mute ramps the volume from any setting to noiseless hard mute state. There are two methods in which the TAS5026A can be placed into mute. The TAS5026A is placed in the noiseless mute when the MUTE terminal is asserted low for a minimum of 3 MCLK_IN cycles. Alternatively, the mute mode can be initiated by setting the mute bit in the system control register through the serial control interface. The TAS5026A is held in mute state as long as the terminal is low or I2C mute setting is active. This command uses quiet entry and exit sequences to and from the hard mute state. SLES068A--February 2003--Revised January 2004 TAS5026A 19 Architecture Overview If an error recovery (described in the PWM section) occurs after a mute request has been received, the device returns from error recovery with the channel volume set as specified by the mute command. 2.3.3 Automute Automute is an automatic sequence that can be enabled or disabled via the serial control interface. The default for this control is enabled. When enabled, the PWM automutes an individual channel when a channel receives from 5 ms to 50 ms of consecutive zeros. This time interval can be selectable using the automute delay register. The default interval is 5 ms at 48 kHz. This duration is independent of the sample rate. The automute state is exited when two consecutive samples of nonzero data are received. The TAS5026A exit from automute is performed quickly and preserves all music information. This mode uses the valid low to provide a low-noise floor while maintaining a short start-up time. Noise free entry and exit is achieved by using the PWM quiet start and stop sequences. 2.3.4 Individual Channel Mute Individual channel mute is invoked through the serial interface. Individual channel mute permits each channel of the TAS5026A to be individually muted and unmuted. The operation that is performed is identical to the mute operation; however, it is performed on a per channel basis. A TAS5026A channel is held in the mute state as long as the serial interface mute setting for that channel is set. 2.3.5 De-Emphasis Filter For audio sources that have been pre-emphasized, a precision 50-s/15-s de-emphasis filter is provided to support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. See Figure 2-11 for a graph showing the de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register. Table 2-10. De-Emphasis Filter Characteristics DEM_SEL2 (MSB) 0 0 1 1 DEM_SEL1 0 1 0 1 DESCRIPTION De-emphasis disabled De-emphasis enabled for Fs = 48 kHz De-emphasis enabled for Fs = 44 kHz De-emphasis enabled for Fs = 32 kHz Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128 LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode. Response - dB 0 De-Emphasis -10 3.18 (50 s) 10.6 (15 s) f - Frequency - kHz Figure 2-11. De-Emphasis Filter Characteristics 2.4 Pulse-Width Modulator (PWM) The TAS5026A contains six channels of high performance digital Equibit PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load) configuration. The TAS5026A device uses noise shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The PWM provides six pseudo-differential outputs to drive six monolithic power stages (such as TAS5110) or six discrete differential power stages using of gate drivers (such as the TAS5182) and MOSFETs in single-ended or bridged configurations. The TAS5026A also provides a high performance differential output that can be used to drive an external analog headphone amplifier. 20 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview 2.4.1 Clipping Indicator The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms. 2.4.2 Error Recovery Error recovery is used to provide error management and to permit the PWM output to be reset while preserving all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit in control register 1. Error recovery is a level sensitive signal. The device also performs an error recovery automatically: * * When the speed configuration is changed to normal, double, or quad speed Following a change in the serial data bus interface configuration When ERR_RCVRY is brought low, all valid signals go low, and the PWM-P and PWM-M outputs go low. If there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization sequence. After the initialization time, the TAS5026A begins normal operation. During error recovery, all controls and device settings that were not updated are maintained in their current configurations. To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay can be selected to be either 6 s or 47 s. During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error recovery register bit is returned to normal operation state. Table 2-11 shows the device output signal states while during error recovery. Table 2-11. Device Outputs During Error Recovery SIGNAL Valid 1-Valid 6 PWM P-outputs PWM M-outputs MCLKOUT SCLK SCLK LRCLK LRCLK SDA CLIP MODE All All All All Master Slave Master Slave All All SIGNAL STATE Low Low Low Low Low Signal input Low Signal input Signal input High The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks. 2.4.3 Individual Channel Error Recovery Individual channel error recovery is used to provide error management and to permit the PWM output to be turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery register to low. While the error recover bits are brought low, the valid signals go to the low state. When the error recovery bits are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation. The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is selectable. This delay can be selected to be either 6 s or 47 s. The TAS5026A controls the relative timing of the pseudo-differential drive control signals plus the valid signal to minimize the production of system noise during error recovery operations. The transitions to valid low and valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks. SLES068A--February 2003--Revised January 2004 TAS5026A 21 Architecture Overview 2.4.4 PWM DC-Offset Correction An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of 1.56% of full scale. The default value is zero correction represented by 00 (hex). These values can be changed at any time through the serial control interface. 2.4.5 Interchannel Delay An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK. Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default values are 0 for the first channel and 76 for each successive channel. These values can be updated upon power up through the serial control interface. This delay is generated in the PWM block with the appropriate control signals generated in the CTL block. These values can be changed at any time through the serial control interface. NOTE: The performance of a PurePath Digital amplifier system is optimized by setting the PWM timing based upon the type of back-end device that is used and the layout. These values are set during initialization using the I2C serial interface. 2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface The TAS5026A provides six PWM outputs, which are designed to drive switching output stages (back-ends) in both single-ended (SE) and H-bridge (bridge tied load) configuration. The back-ends may be monolithic power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the the TAS55182) and MOSFETs in single-ended or bridged configurations. The TAS5110 device is optimized for bridge tied load (BTL) configurations. These devices require a pure differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110 OUTA and OUTB are both low. One Channel of TAS5026A PWM_AP PWM_AM VALID AP AM RESET BP BM OUTB Speaker TAS5110 OUTA Figure 2-12. PWM Outputs and H-Bridge Driven in BTL Configuration 2.5 I2C Serial Control Interface MCLK must be active for the TAS5026A to support I2C bus transactions. The TAS5026A has a bidirectional serial control interface that is compatible with the I2C (Inter IC) bus protocol and supports both 100 KBPS and 400 kbps data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multi-master bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The TAS5026A supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation (400 kHz maximum). The TAS5026A performs all I2C operations without I2C wait cycles. PurePath Digital is a trademark of Texas Instruments. 22 TAS5026A SLES068A--February 2003--Revised January 2004 Architecture Overview The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 2-13. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5026A holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. I2C An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus. SDA R/ A 8 Bit Register Address (N) W 8 Bit Register Data For Address (N) 8 Bit Register Data For Address (N) 7 Bit Slave Address A A A 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SCL Start Stop Figure 2-13. Typical I2C Sequence There are no limits on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is also shown in Figure 2-13. The 7-bit address for the TAS5026A is 001101X, where X is a programmable address bit. Using the CS0 terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system. These two addresses are licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the TAS5026A, the I2C master uses 0011010 if CS0 = 0 and 0011011 if CS0 = 1. In addition to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register location within the device interface. Read and write operations to the TAS5026A can be done using single byte or multiple byte data transfers. 2.5.1 Single-Byte Write As shown in Figure 2-14, a single byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device address and the read/write bit, the TAS5026A device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5026A internal memory address being accessed. After receiving the address byte, the TAS5026A again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5026A again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single byte data write transfer. SLES068A--February 2003--Revised January 2004 TAS5026A 23 Architecture Overview Start Condition Acknowledge Acknowledge Acknowledge A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK I2C Device Address and Read/Write Bit Register Address Data Byte Stop Condition Figure 2-14. Single-Byte Write Transfer 2.5.2 Multiple-Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to TAS5026A as shown in Figure 2-15. After receiving each data byte, the TAS5026A responds with an acknowledge bit. Start Condition Acknowledge Acknowledge Acknowledge Acknowledge A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D6 D1 D0 ACK D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Register Address First Data Byte Other Data Bytes Last Data Byte Stop Condition Figure 2-15. Multiple-Byte Write Transfer 2.5.3 Single-Byte Read As shown in Figure 2-16, a single byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is 0. After receiving the TAS5026A address and the read/write bit, the TAS5026A responds with an acknowledge bit. Also, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5026A address and the read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5026A and the read/write bit, the TAS5026A again responds with an acknowledge bit. Next, the TAS5026A transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Not Acknowledge A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Register Address I2C Device Address and Read/Write Bit Data Byte Stop Condition Figure 2-16. Single-Byte Read 2.5.4 Multiple-Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TAS5026A to the master device as shown in Figure 2-17. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Not Acknowledge A6 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Register Address I2C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition Figure 2-17. Multiple-Byte Read 24 TAS5026A SLES068A--February 2003--Revised January 2004 Serial Control Interface Register Definitions 3 Serial Control Interface Register Definitions Table 3-1 shows the register map for the TAS5026A. Default values in this section are in bold. Table 3-1. I2C Register Map ADDR HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 Error status register System control register 0 System control register 1 Error recovery register Automute delay DC-offset control register channel 1 DC-offset control register channel 2 DC-offset control register channel 3 DC-offset control register channel 4 DC-offset control register channel 5 DC-offset control register channel 6 Interchannel delay register channel 1 Interchannel delay register channel 2 Interchannel delay register channel 3 Interchannel delay register channel 4 Interchannel delay register channel 5 Interchannel delay register channel 6 Reserved Volume control register channel 1 Volume control register channel 2 Volume control register channel 3 Volume control register channel 4 Volume control register channel 5 Volume control register channel 6 Individual channel mute DESCRIPTION General status register The volume table is contained in Appendix A. Default values are shown in bold in the following tables. SLES068A--February 2003--Revised January 2004 TAS5026A 25 Serial Control Interface Register Definitions 3.1 General Status Register (0x00) Table 3-2. General Status Register (Read Only) D7 0 1 - D6 0 - D5 1 - D4 0 - D3 0 - D2 1 - D1 1 - D0 0 1 No volume update is in progress. Volume update is in progress. Always 0 Device identification code FUNCTION Any valid signal is inactive (see status register (0x03)) (see Note 1). No internal errors (all valid signals are high) NOTE 1: This bit is reset automatically when one or more channels are active. 3.2 Error Status Register (0x01) Table 3-3. Error Status Register D7 1 0 D6 1 0 D5 0 D4 1 0 D3 1 0 D2 1 0 D1 1 0 D0 1 0 FS error has occurred Control pin change has occurred LRCLK error MCLK_IN count error FUNCTION DCLK phase error with respect to MCLK_IN MCLK_IN phase error with respect to DCLK PWM timing error No errors--no control pins changed NOTE 2: Write 00 hex to clear error indications in error status register. 3.3 System Control Register 0 (0x02) Table 3-4. System Control Register 0 D7 0 0 1 1 - D6 0 1 0 1 - D5 0 1 - D4 0 0 1 1 - D3 0 1 0 1 - D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Double speed Quad speed Illegal Use de-emphasis pin controls Use de-emphasis I2C controls No de-emphasis De-emphasis for Fs = 32 kHz De-emphasis for Fs = 44.1 kHz De-emphasis for Fs = 48 kHz 16 bit, MSB first; right justified 20 bit, MSB first; right justified 24 bit, MSB first; right justified 16-bit I2S 20-bit I2S 24-bit I2S 16-bit MSB first 16-bit DSP Frame FUNCTION Normal mode (in slave mode--quad speed detected if MCLK_IN = 128 Fs) 26 TAS5026A SLES068A--February 2003--Revised January 2004 Serial Control Interface Register Definitions 3.4 D7 0 - System Control Register 1 (0x03) Table 3-5. System Control Register 1 D6 0 1 D5 0 1 D4 0 1 D3 0 1 D2 0 1 D1 0 1 D0 1 Reserved Valid remains high during automute. Valid goes low during automute. Valid remains high during mute. Valid goes low during mute. Mute Normal mode Set error recovery delay at 6 s Set error recovery delay at 47 s Error recovery (forces error recovery initialization sequence) Normal mode Automute disabled Automute enabled Reserved FUNCTION 3.5 D7 1 0 Error Recovery Register (0x04) Table 3-6. Error Recovery Register D6 1 - D5 - - D4 - - D3 - - D2 - - D1 - - D0 - - if 0x84 is written into 0x1F - Enable volume ramp up after an error recovery sequence initiated by the ERR_RCVRY terminal or the I2C error recovery command (register 0x03 bit D2). FUNCTION Set to 11 under default conditions and when x00 is written into 0x1F 1 - - - - - - - if 0x84 is written into 0x1F - Disable volume ramp up after an error recovery sequence initiated by the ERR_RCVRY terminal or the I2C error recovery command (register 0x03 bit D2) - 0 - - - - - - if 0x84 is written into 0x1F - Enable volume ramp up after error recovery sequence initiated by register bits D5-D0 of this register. - 1 - - - - - - if 0x84 is written into 0x1F - Enable volume ramp up after error recovery sequence initiated by register bits D5-D0 of this register. - - - - - - - - - - - - - - 0 - - - - - 1 - 0 - - - - 1 - - 0 - - - 1 - - - 0 - - 1 - - - - 0 - 1 - - - - - 0 1 Put channel 6 into error recovery mode Put channel 5 into error recovery mode Put channel 4 into error recovery mode Put channel 3 into error recovery mode Put channel 2 into error recovery mode Put channel 1 into error recovery mode Normal operation SLES068A--February 2003--Revised January 2004 TAS5026A 27 Serial Control Interface Register Definitions 3.6 D7 0 - Automute Delay Register (0x05) Table 3-7. Automute Delay Register D6 0 D5 0 D4 0 D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 Reserved Set automute delay at 5 ms Set automute delay at 10 ms Set automute delay at 15 ms Set automute delay at 20 ms Set automute delay at 25 ms Set automute delay at 30 ms Set automute delay at 35 ms Set automute delay at 40 ms Set automute delay at 45 ms Set automute delay at 50 ms FUNCTION 3.7 DC-Offset Control Registers (0x06-0x0B) Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0A, and 0x0B). Table 3-8. DC-Offset Control Registers D7 1 0 0 D6 0 0 1 D5 0 0 1 D4 0 0 1 D3 0 0 1 D2 0 0 1 D1 0 0 1 D0 0 0 1 No dc-offset correction FUNCTION Maximum correction for positive dc offset (-1.56% FS) Maximum correction for negative dc offset (1.56% FS) 3.8 Interchannel Delay Registers (0x0C-0x11) Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0C, 0x0D, 0x0E, 0x0F, 0x10, and 0x11). The first channel delay is set at 0. Each subsequent channel has a default value that is 76 DCLKs larger than the preceding channel. Table 3-9. Six Interchannel Delay Registers D7 0 0 1 1 0 0 1 D6 0 1 0 1 0 1 1 D5 0 0 0 1 1 1 1 D4 0 0 1 0 1 1 1 D3 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 1 D1 0 0 0 0 0 0 1 D0 0 0 0 0 0 0 1 Default for channel 2 Default for channel 3 Default for channel 4 Default for channel 5 Default for channel 6 FUNCTION Minimum absolute delay, 0 DCLK cycles, default for channel 1 Maximum absolute delay, 255 DCLK cycles 28 TAS5026A SLES068A--February 2003--Revised January 2004 Serial Control Interface Register Definitions 3.9 D7 1 - Individual Channel Mute Register (0x19) Table 3-10. Individual Channel Mute Register D6 1 D5 1 0 D4 1 0 D3 1 0 D2 1 0 D1 1 0 D0 1 0 Reserved No channels are muted Mute channel 1 Mute channel 2 Mute channel 3 Mute channel 4 Mute channel 5 Mute channel 6 FUNCTION SLES068A--February 2003--Revised January 2004 TAS5026A 29 Serial Control Interface Register Definitions 30 TAS5026A SLES068A--February 2003--Revised January 2004 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes 4 4.1 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes System Initialization Reset is used during system initialization to hold the TAS5026A inactive while power (VDD), the master clock (MCLK_IN), the device control, and the data signals become stable. The recommended initialization sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control signals (MUTE, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable. Figure 4-1 shows the recommended sequence and timing for the RESET terminal relative to system VDD voltage and MCLK. 3V VDD RESET 24 MCLK_IN Cycles MCLK Figure 4-1. RESET During System Initialization Within the first 2 ms following the low to high transition of the RESET terminal, the serial data interface format should be set in the serial data interface control register using the I2C serial control interface. If the data rate setting is other than the setting specified by the DBSPD terminal, then the data rate should be set using the DBSPD terminal or I2C interface within 2 ms, following the low to high transition of the RESET terminal. The time available to set the I2C registers following the low to high transition of the RESET terminal can be extended using the ERR_RCVRY terminal. While ERR_RCVRY is low, the TAS5026A outputs are held inactive. Once the I2C control registers are set, the ERR_RCVRY terminal can be released and the TAS5026A starts operation. Figure 4-2 shows how ERR_RCVRY terminal can be used to extend the interval as long as necessary to set the I2C registers following the low-to-high transition of the RESET terminal. SLES068A--February 2003--Revised January 2004 TAS5026A 31 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes MCLK RESET < 2 ms ERR_RCVRY ERR_RCVRY and MUTE can be set at any time prior to 2 ms following the low-to-high transition of RESET MUTE > 5 ms Volume ramp up 120 ms Wait a minimum of 100 s after the low-to-high transition of RESET Set serial interface format, data rate, volume, ... via I2C Release ERR_RCVRY and then MUTE when I2C registers are programmed Figure 4-2. Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal The operation of the TAS5026A can be tailored as desired to meet specific operating requirements by adjusting the following: * * * * * * Volume Data sample rate Emphasis/deemphasis settings Individual channel mute Automute delay register DC-offset control registers If desired, the TAS5026A can be set to perform an unmute sequence following the low-to-high transition of the ERR_RCVRY terminal or the error recovery I2C command (register X03 bit D2). This capability is set by writing x7F to the individual error recovery register (x04) and an x84 to x1F (a feature enable register). 4.2 Data Sample Rate If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control register. If it is known at least 60 ms in advance that the sample rate changes, mute can be used to provide a completely silent transition. The timing of this control sequence is shown in Figure 4-3 and Figure 4-4. 32 TAS5026A SLES068A--February 2003--Revised January 2004 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes Clock Transition Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Change to a 48-kHz data rate MCLK_IN = 12.288 MHz MCLK > 5 ms MUTE Terminal Volume Ramp Down 42 - 65 ms Volume Ramp Up 42 - 65 ms DBSPD Terminal Set within 2 ms of transition < 2 ms < 2 ms Figure 4-3. Changing the Data Sample Rate Using the DBSPD Terminal Clock Transition Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Change to a 48-kHz data rate MCLK_IN = 12.288 MHz MCLK > 5 ms MUTE Terminal Volume Ramp Down 42 - 65 ms < 2 ms Set data rate via I2C register 0x02, D7 and D6 ERR_RCVRY Terminal Hold ERR_RCVRY low to give additional timeset registers < 2 ms Volume Ramp Up 42 - 65 ms Figure 4-4. Changing the Data Sample Rate Using the I2C However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then RESET should be applied during this time. There are two recommended control procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences are shown in Figure 4-5 and Figure 4-6. Because this sequence employs the RESET terminal, the internal register settings are set to the default values. SLES068A--February 2003--Revised January 2004 TAS5026A 33 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes Figure 4-5 shows the procedure to change the data rate using the DBSPD terminal and then to restore the register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET is released. This permits the system controller to have as much additional time as necessary to restore the register settings. Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system re-initializes. Clock unstable during transition. HIGH and LOW intervals < 20 ns Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Change to a 48-kHz data rate MCLK_IN = 12.288 MHz MCLK > 5 ms MUTE Terminal Volume Ramp Down 60 ms Volume Ramp Up 120 ms RESET Terminal DBSPD Terminal Wait a minimum of 100 s to set DBSPD ERR_RCVRY Terminal < 2 ms ERR_RCVRY can be set at any time within this interval Wait a minimum of 100 s after the LOW to HIGH transition of RESET Restore register settings via I2C Release ERR_RCVRY and then MUTE when I2C registers are programmed Figure 4-5. Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal Because this sequence employs the RESET terminal, the internal register settings are set to the default values. Figure 4-5 shows the procedure to change the data rate using register 0x02 bits D7 and D6 and then to restore the other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET is released. This permits the system controller to have as much additional time as necessary to restore the register settings. Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system re-initializes. 34 TAS5026A SLES068A--February 2003--Revised January 2004 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes Clock unstable during transition. HIGH and LOW intervals < 20 ns Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Change to a 48-kHz data rate MCLK_IN = 12.288 MHz MCLK > 5 ms MUTE Terminal Volume Ramp Down 60 ms Volume Ramp Up 120 ms RESET Terminal < 2 ms ERR_RCVRY Terminal Release ERR_RCVRY and then MUTE when I2C registers are programmed ERR_RCVRY can be set at any time within this interval Wait a minimum of 100 s after the LOW to HIGH transition of RESET Set data rate and restore other register settings via I2C Figure 4-6. Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C 4.3 Changing Between Master and Slave Modes The master and slave mode is set while the RESET terminal is active. Because this sequence employs the RESET terminal the internal register settings are set to the default values. Figure 4-7 shows the procedure to switch between master and slave modes and then restore the register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET is released. This permits the system controller to have as much additional time as necessary to restore the register settings. Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system re-initializes. SLES068A--February 2003--Revised January 2004 TAS5026A 35 System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes Clock unstable during transition. Change from Master Mode Change to Slave Mode MCLK > 5 ms MUTE Terminal Volume Ramp Down 60 ms Volume Ramp Up 120 ms RESET Terminal M_S Terminal Wait a minimum of 100 s to set M_S ERR_RCVRY Terminal < 2 ms ERR_RCVRY can be set at any time within this interval Wait a minimum of 100 s after the LOW to HIGH transition of RESET Release ERR_RCVRY and then MUTE when I2C registers are programmed Restore register settings via I2C Figure 4-7. Changing Between Master and Slave Clock Modes 36 TAS5026A SLES068A--February 2003--Revised January 2004 Specifications 5 5.1 Specifications Absolute Maximum Ratings Over Operating Temperature Ranges (Unless Otherwise Noted) Digital supply voltage range: DVDD_CORE, DVDD_PWM, DVDD_RCL . . . . . . . . . . . . . . . . . . -0.3 V to 4.2 V Analog supply voltage range: AVDD_PLL, ADD_OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.2 V Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDDX + 0.3 V Operating free-air temperature, TAS5026A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions MIN TYP 3.3 60 25 200 100 3 3.3 10 25 35 100 3.6 MAX 3.6 UNIT V mA A mW W V mA A mW W Digital Digital Digital Analog Analog Analog DVDDX, See Note 1 Operating Power down, See Note 2 Operating Power down AVDDX, See Note 3 Operating Power down, See Note 2 Operating Power down, See Note 2 3 Supply voltage Supply current Power dissipation Supply voltage Supply current Power dissipation NOTES: 3. DVDD_CORE, DVDD_PWM, DVDD_RCL 4. If the clocks are turned off. 5. AVDD_PLL, AVDD_OSC 5.3 5.3.1 Electrical Characteristics Over Recommended Operating Conditions Static Digital Specifications Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN 2 0 IO = -1 mA IO = 4 mA 2.4 0.4 -10 10 MAX DVDD1 0.8 UNIT V V V V A High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current VIH VIL VOH VOL Ilkg 5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended Operating Conditions (Unless Otherwise Noted) (Fs = 48 kHz) PARAMETER TEST CONDITIONS MIN 0 0.012 24.1 24.1 kHz to 152.3 kHz 50 700 0.93% TYP MAX 20 UNIT kHz dB kHz dB s Pass band Pass band ripple Stop band Stop band attenuation Group delay PWM modulation index (gain) SLES068A--February 2003--Revised January 2004 TAS5026A 37 Specifications 5.3.3 TAS5026A/TAS5110 System Performance Measured at the Speaker Terminals Over Recommended Operating Conditions (Unless Otherwise Noted), (Fs = 48 kHz) PARAMETER TEST CONDITIONS A-weighted A-weighted, -60 dB, f = 1 kHz, 20 Hz-20 kHz 0 dB, 1 kHz, 20 Hz-20 kHz MIN TYP 93 94 0.09% MAX UNIT dB dB SNR (EIAJ) Dynamic range THD+N 5.4 5.4.1 Switching Characteristics Command Sequence Timing Reset Timing--RESET PARAMETER TEST CONDITIONS MIN 50 1 4 42 5 65 TYP MAX UNIT ns s ms ms 5.4.1.1 CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED) tw(RESET) tp(VALID_LOW) tp(VALID_HIGH) td(VOLUME) Pulses duration, RESET active Propagation delay Propagation delay Delay time RESET tw(RESET) VALID 1-6 VOLUME 1-6 tp(VALID_LOW) td(VOLUME) tp(VALID_HIGH) Figure 5-1. RESET Timing 38 TAS5026A SLES068A--February 2003--Revised January 2004 Specifications 5.4.1.2 Power-Down Timing--PDN 5.4.1.2.1 Long Recovery CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED) PARAMETER tw(PDN) td(R PDNR) tp(VALID_LOW) tp(VALID_HIGH) td(VOLUME) td(R PDNR) Pulse duration, PDN active Reset high to PDN rising edge TEST CONDITIONS MIN 50 16 MCLKs 1 85 42 100 65 TYP MAX UNIT ns ns s ms ms RESET PDN tw(PDN) VALID 1-6 VOLUME 1-6 Normal Operation Normal Operation tp(VALID_HIGH) tp(VALID_LOW) td(VOLUME) Figure 5-2. Power-Down and Power-Up Timing--RESET Preceding PDN SLES068A--February 2003--Revised January 2004 TAS5026A 39 Specifications 5.4.1.2.2 Short Recovery CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED) PARAMETER tw(PDN) td(R PDNR) tp(VALID_LOW) tp(VALID_HIGH) td(VOLUME) td(R PDNR) Pulse duration, PDN active PDN high to reset rising edge TEST CONDITIONS MIN 50 16 MCLKs 1 4 42 5 65 TYP MAX UNIT ns ns s ms ms RESET PDN tw(PDN) VALID 1-6 VOLUME 1-6 Normal Operation Normal Operation tp(VALID_HIGH) tp(VALID_LOW) td(VOLUME) Figure 5-3. Power-Down and Power-Up Timing--RESET Following PDN 5.4.1.3 Error Recovery Timing--ERR_RCVRY PARAMETER TEST CONDITIONS MIN 5 MCLKs 6 4 47 5 TYP MAX UNIT ns s ms CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED) tw(ER) tp(VALID_LOW) tp(VALID_HIGH) Pulse duration, ERR_RCVRY active Selectable for minimum or maximum 40 TAS5026A SLES068A--February 2003--Revised January 2004 Specifications tw(ER) ERR_RCVRY VALID 1-6 Normal Operation Normal Operation tp(VALID_HIGH) tp(VALID_LOW) Figure 5-4. Error Recovery Timing 5.4.1.4 MUTE Timing--MUTE PARAMETER TEST CONDITIONS MIN 3 MCLKs 42 tw(MUTE) TYP MAX UNIT ns ms CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED) tw(MUTE) td(VOL) Pulse duration, PDN active MUTE VOLUME VALID 1-6 Normal Operation Normal Operation td(VOL) td(VOL) Figure 5-5. Mute Timing SLES068A--February 2003--Revised January 2004 TAS5026A 41 Specifications 5.4.2 Serial Audio Port 5.4.2.1 Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER f(SCLK) tsu(SDIN) th(SDIN) f(LRCLK) Frequency, SCLK SDIN setup time before SCLK rising edge SDIN hold time before SCLK rising edge LRCLK frequency MCLK_IN duty cycle SCLK duty cycle LRCLK duty cycle tsu(LRCLK) LRCLK setup time before SCLK rising edge MCLK high and low time 20 20 20 10 32 48 50% 50% 50% ns ns 192 MIN TYP MAX 12.288 UNIT MHz ns ns kHz 5.4.2.2 Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER MIN 0 0 TYP MAX 5 5 UNIT ns ns MCLK_IN to SCLK MCLK_IN to LRCLK t(MSD) t(MLRD) 5.4.2.3 DSP Serial Interface Mode Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER MIN TYP MAX 12.288 UNIT MHz ns 1/(64xFs) 20 10 50% ns ns ns SCLK frequency Delay time, SCLK rising to Fs Pulse duration, sync SDIN and LRCLK setup time before SCLK falling edge SDIN and LRCLK hold time from SCLK falling edge SCLK duty cycle f(SCLK) td(FS) tw(FSHIGH) tsu(SDIN) th(SDIN) SCLK th(SDIN) tsu(SDIN) SDIN Figure 5-6. Right-Justified, I2S, Left-Justified Serial-Protocol Timing 42 TAS5026A SLES068A--February 2003--Revised January 2004 Specifications SCLK tsu(LRCLK) LRCLK NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns). Figure 5-7. Right, Left, and I2S Serial-Mode Timing Requirement SCLK LRCLK t(MRLD) t(MSD) MCLK Figure 5-8. Serial Audio Ports Master-Mode Timing SCLK tsu(LRCLK) th(LRCLK) LRCLK tw(FSHIGH) tsu(SDIN) SDIN th(SDIN) Figure 5-9. DSP Serial-Port Timing SLES068A--February 2003--Revised January 2004 TAS5026A 43 Specifications SCLK 64 SCLKS LRCLK tw(FSHIGH) SDIN 16 Bits Left Channel 16 Bits Right Channel 32 Bits Unused Figure 5-10. DSP Serial-Port Expanded Timing SCLK tsu(SDIN) = 20 ns th(SDIN) = 10 ns SDIN Figure 5-11. DSP Absolute Timing 44 TAS5026A SLES068A--February 2003--Revised January 2004 Specifications 5.4.3 Serial Control Port--I 2C Operation 5.4.3.1 Timing Characteristics for I2C Interface Signals Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER fSCL tw(H) tw(L) tr tf tsu1 th1 t(buf) tsu2 th2 tsu3 CL Frequency, SCL Pulse duration, SCL high Pulse duration, SCL low Rise time, SCL and SDA Fall time, SCL and SDA Setup time, SDA to SCL Hold time, SCL to SDA Bus free time between stop and start condition Setup time, SCL to start condition Hold time, start condition to SCL Setup time, SCL to stop condition Load capacitance for each bus line 250 0 4.7 4.7 4 4 400 TEST CONDITIONS STANDARD MODE MIN 0 4 4.7 1000 300 100 0 1.3 0.6 0.6 0.6 400 MAX 100 FAST MODE MIN 0 0.6 1.3 300 300 MAX 400 kHz s s ns ns ns ns s s s s pF UNIT tw(H) tw(L) tr tf SCLK tsu th1 SDA Figure 5-12. SCL and SDA Timing SCLK th2 tsu2 t(buf) tsu3 SDA Start Condition Stop Condition Figure 5-13. Start and Stop Conditions Timing SLES068A--February 2003--Revised January 2004 TAS5026A 45 Specifications 46 TAS5026A SLES068A--February 2003--Revised January 2004 6 AVDD_PLL AVSS_PLL VREGA_CAP VREGB_CAP DVDD_RCL DVSS_RCL VREGC_CAP DVDD_PWM DVSS_PWM Power Supply CLKOUT XTAL_OUT XTAL_IN PWM Section PWM_AP_1 PWM Ch. PWM_AM_1 VALID_1 M_S PLL_FLT_1 PLL_FLT_2 SCLK LRCLK MCLK_IN P1.4/SMCLK/TCK Output Control SLES068A--February 2003--Revised January 2004 Application Information DA610 DSP ACLKX AFSX TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET PWM_AP_2 PWM_AM_2 Clock, PLL and Serial Data I/F Signal Processing PWM Ch. ALKX0 ALKX1 ALKX2 MCLKOUT SDIN1 SDIN2 SDIN3 VALID_2 TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET PWM AP_3 PWM AM_3 VALID_3 DM_SEL1 DM_SEL2 DBSPD PWM Ch. TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET PWM_AP_4 P1.5/IA1/TDI SDA SCL CSO Serial Control I/F Auto Mute De-Emphasis Soft Volume Error Recovery Soft Mute Clip Detect PWM Ch. PWM_AM_4 VALID_4 TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET PWM_AP_5 PWM_AM_5 PWM Ch. VALID_5 Figure 6-1. Typical TAS5026A Application RESET PDN Reset, Pwr Dwn and Status PWM Ch. CLIP MUTE ERR_RCVRY MSP430 P1.0 P1.1 P1.2 TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET PWM_AP_6 PWM_AM_6 VALID_6 P1.3 TAS5110 PWAP H-Bridge PWAM PWBM PWBP SHUTDOWN RESET P2.0 Application Information TAS5026A 47 Application Information 6.1 Serial Audio Interface Clock Master and Slave Interface Configuration 6.1.1 Slave Configuration Other Digital Audio Sources DA610 DSP (Master Mode) 12.288 MHz XTAL TAS5026A (Slave Mode) PCM1800 ADC OSCI OSCO GND XTALI XTALO SDIN1 SDIN2 SDIN3 Left Analog Right Analog DOUT ALKR0 ALKR1 ALKR2 ALKX0 ALKX1 ALKX2 BCK LRCK SYSCLK ACLKR AFSR CLKIN ACLKX AFSX CLKOUT SCLK LRCK MCLKO MCLKO NC Figure 6-2. TAS5026A Serial Audio Port--Slave-Mode Connection Diagram 6.1.2 Master Configuration Other Digital Audio Sources DA610 DSP TAS5026A (Master Mode) PCM1800 ADC 12.288 MHz XTAL ALKR0 ALKR1 ALKR2 ALKX0 ALKX1 ALKX2 XTALI XTALO SDIN1 SDIN2 SDIN3 Left Analog Right Analog DOUT BCK LRCK SYSCLK ACLKR AFSR CLKIN ACLKX AFSX CLKOUT GND MCLKO SCLK LRCK MCLKO Figure 6-3. TAS5026A Serial Audio Port--Master-Mode Connection Diagram 48 TAS5026A SLES068A--February 2003--Revised January 2004 Mechanical Data 7 Mechanical Data PLASTIC QUAD FLATPACK 0,27 0,17 48 33 PAG (S-PQFP-G64) 0,50 0,08 M 49 32 64 17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0-7 0,75 0,45 16 1,20 MAX 0,08 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 SLES068A--February 2003--Revised January 2004 TAS5026A 49 Mechanical Data 50 TAS5026A SLES068A--February 2003--Revised January 2004 Appendix A--Volume Table Appendix A--Volume Table VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 1111 1001 1111 1000 1111 0111 1111 0110 1111 0101 1111 0100 1111 0011 1111 0010 1111 0001 1111 0000 1110 1111 1110 1110 1110 1101 1110 1100 1110 1011 1110 1010 1110 1001 1110 1000 1110 0111 1110 0110 1110 0101 1110 0100 1110 0011 1110 0010 1110 0001 1110 0000 1101 1111 1101 1110 1101 1101 1101 1100 1101 1011 1101 1010 1101 1001 1101 1000 1101 0111 1101 0110 1101 0101 1101 0100 1101 0011 1101 0010 1101 0001 1101 0000 1100 1111 1100 1110 24 23.5 23 22.5 22 21.5 21 20.5 20 19.5 19 18.5 18 17.5 170 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 GAIN dB VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 1100 1101 1100 1100 1100 1011 1100 1010 1100 1001 1100 1000 1100 0111 1100 0110 1100 0101 1100 0100 1100 0011 1100 0010 1100 0001 1100 0000 1011 1111 1011 1110 1011 1101 1011 1100 1011 1011 1011 1010 1011 1001 1011 1000 1011 0111 1011 0110 1011 0101 1011 0100 1011 0011 1011 0010 1011 0001 1011 0000 1010 1111 1010 1110 1010 1101 1010 1100 1010 1011 1010 1010 1010 1001 1010 1000 1010 0111 1010 0110 1010 0101 1010 0100 1010 0011 1010 0010 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 -10 -10.5 -11 -11.5 -12 -12.5 -13 -13.5 -14 -14.5 -15 -15.5 -16 -16.5 -17 -17.5 -18 -18.5 -19 -19.5 GAIN dB SLES068A--February 2003--Revised January 2004 TAS5026A 51 Appendix A--Volume Table VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 1010 0001 1010 0000 1001 1111 1001 1110 1001 1101 1001 1100 1001 1011 1001 1010 1001 1001 1001 1000 1001 0111 1001 0110 1001 0101 1001 0100 1001 0011 1001 0010 1001 0001 1001 0000 1000 1111 1000 1110 1000 1101 1000 1100 1000 1011 1000 1010 1000 1001 1000 1000 1000 0111 1000 0110 1000 0101 1000 0100 1000 0011 1000 0010 1000 0001 1000 0000 0111 1111 0111 1110 0111 1101 0111 1100 0111 1011 0111 1010 0111 1001 0111 1000 0111 0111 0111 0110 0111 0101 -20 -20.5 -21 -21.5 -22 -22.5 -23 -23.5 -24 -24.5 -25 -25.5 -26 -26.5 -27 -27.5 -28 -28.5 -29 -29.5 -30 -30.5 -31 -31.5 -32 -32.5 -33 -33.5 -34 -34.5 -35 -35.5 -36 -36.5 -37 -37.5 -38 -38.5 -39 -39.5 -40 -40.5 -41 -41.5 -42 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 0111 0100 0111 0011 0111 0010 0111 0001 0111 0000 0110 1111 0110 1110 0110 1101 0110 1100 0110 1011 0110 1010 0110 1001 0110 1000 0110 0111 0110 0110 0110 0101 0110 0100 0110 0011 0110 0010 0110 0001 0110 0000 0101 1111 0101 1110 0101 1101 0101 1100 0101 1011 0101 1010 0101 1001 0101 1000 0101 0111 0101 0110 0101 0101 0101 0100 0101 0011 0101 0010 0101 0001 0101 0000 0100 1111 0100 1110 0100 1101 0100 1100 0100 1011 0100 1010 0100 1001 0100 1000 -42.5 -43 -43.5 -44 -44.5 -45 -45.5 -46 -46.5 -47 -47.5 -48 -48.5 -49 -49.5 -50 -50.5 -51 -51.5 -52 -52.5 -53 -53.5 -54 -54.5 -55 -55.5 -56 -56.5 -57 -57.5 -58 -58.5 -59 -59.5 -60 -60.5 -61 -61.5 -62 -62.5 -63 -63.5 -64 -64.5 GAIN dB GAIN dB 52 TAS5026A SLES068A--February 2003--Revised January 2004 Appendix A--Volume Table VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 0100 0111 0100 0110 0100 0101 0100 0100 0100 0011 0100 0010 0100 0001 0100 0000 0011 1111 0011 1110 0011 1101 0011 1100 0011 1011 0011 1010 0011 1001 0011 1000 0011 0111 0011 0110 0011 0101 0011 0100 0011 0011 0011 0010 0011 0001 0011 0000 0010 1111 0010 1110 0010 1101 0010 1100 0010 1011 0010 1010 0010 1001 0010 1000 0010 0111 0010 0110 0010 0101 -65 -65.5 -66 -66.5 -67 -67.5 -68 -68.5 -69 -69.5 -70 -70.5 -71 -71.5 -72 -72.5 -73 -73.5 -74 -74.5 -75 -75.5 -76 -76.6 -77 -77.5 -78 -78.5 -79 -79.6 -80.1 -80.6 -81.1 -81.5 -82.1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VOLUME SETTING REGISTER VOLUME (BIN) D7 - D0 0010 0100 0010 0011 0010 0010 0010 0001 0010 0000 0001 1111 0001 1110 0001 1101 0001 1100 0001 1011 0001 1010 0001 1001 0001 1000 0001 0111 0001 0110 0001 0101 0001 0100 0001 0011 0001 0010 0001 0001 0001 0000 0000 1111 0000 1110 0000 1101 0000 1100 0000 1011 0000 1010 0000 1001 0000 1000 0000 0111 0000 0110 0000 0101 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 -82.6 -83 -83.5 -84 -84.6 -85.1 -85.8 -86.1 -86.8 -87.2 -87.5 -88.4 -88.8 -89.3 -89.8 -90.3 -90.9 -91.5 -92.1 -92.8 -93.6 -94.4 -95.3 -96.3 -97.5 -98.8 -100.4 -102.4 -104.9 -108.4 -114.4 MUTE MUTE MUTE MUTE MUTE MUTE GAIN dB GAIN dB SLES068A--February 2003--Revised January 2004 TAS5026A 53 Appendix A--Volume Table 54 TAS5026A SLES068A--February 2003--Revised January 2004 PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2005 PACKAGING INFORMATION Orderable Device TAS5026APAG TAS5026APAGR TAS5026APAGRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE Package Type TQFP TQFP TQFP Package Drawing PAG PAG PAG Pins Package Eco Plan (2) Qty 64 64 64 160 1500 Green (RoHS & no Sb/Br) None Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-4-260C-72 HR Level-2-235C-1 YEAR Level-4-260C-72 HR 1500 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996 PAG (S-PQFP-G64) 0,50 48 33 0,27 0,17 PLASTIC QUAD FLATPACK 0,08 M 49 32 64 17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 16 1,20 MAX 0,08 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 WWW..COM Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www..com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com |
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